1. Field of the Invention
The present invention generally relates to DRAMs, and particularly relates to a DRAM having an interface that is equivalent to that of SRAMs.
2. Description of the Related Art
SRAMs (static random access memories) are mainly used as memory devices in the certain type of electronic equipment such as cellular phones. In general, however, SRAMs have low circuit density, so that a cost increase is on a large scale when there is a need to increase memory size. On the other hand, DRAMs (dynamic random access memories) are suitable for the purpose of achieving large memory size at low costs. Accordingly, it is desirable to provide a DRAM having an interface equivalent to that of SRAMs in order to utilize the accumulated asset of existing systems based on the use of SRAMs.
There are several aspects in which the control scheme is different between DRAMs and SRAMs. One of such differences is a timing specification that defines the timing of address inputs for data write/read operations. In the SRAMs, memory cells are comprised of flip-flops, thereby allowing a non-destructive data read operation that does not destroy memory contents at the time of memory access. A memory cell position from which data is retrieved and output to the exterior of the device during a read operation thus changes by following changes in input addresses, and so does a memory cell position at which data is written after the inputting of data from the exterior of the device during a write operation. When there is a command input, and the address is retained for a predetermined time period, then, the address becomes a valid address to be accessed. In this manner, a decision as to whether access is made to a specified address is determined after the predetermined time period following the storing of the specified address.
DRAM memory cells, on the other hand, only allow a destructive read operation that destroys the data contents at the time of memory access. In the DRAMs, therefore, it is necessary to restore the data of sense amplifiers in the memory cells at the time of memory access. During this restore operation, the read address cannot be changed to access different memory cells. The address supplied at the start of data read/write operation is thus stored in internal latches, thereby keeping the latched address unchanged during the read/write to the cell. In this manner, the address and data are fixed at the start of an access operation, and it is rather difficult to fix them a predetermined time after the start of access.
When there is a need to provide compatibility between the DRAM and the SRAM as described above, a write operation presents a major problem. As for a read operation, data outputs can be obtained with some delay from the inputting of an address to the DRAM such that the delay is compatible with the delay from the inputting of an address to the SRAM to the outputting of data. In the case of a write operation, however, an access to a specified address becomes valid only after the address is retained for a predetermined time period and data inputs are fixed. If an attempt is made in the DRAM to write data at the address that is given when the data inputs are fixed, a series of write operation steps must be started after this timing, resulting in the write operation being carried out in the following command cycle. If the operation of the following command cycle is a read operation or the like that begins immediately after the inputting of a command, the read operation of this cycle clashes with the write operation that is delayed from the previous cycle. This results in either one of these operations being not performed.
In order to obviate this, DRAMs having an equivalent interface to SRAMs typically have a buffer that temporarily store data and an address supplied from the exterior of the device, and the data of the buffer is stored in the specified memory cells at the time of a next write operation. Namely, the data and address entered from the exterior of the device at the time of a first write operation are temporarily stored in the buffer when the data and address are fixed, and the data of the buffer is written at the memory cell position specified by the address of the buffer at the time of a second write operation. Data and an address newly entered with reference to the second write operation are stored in the buffer when the data and address are fixed, thereby preparing for a next (third) write operation.
In this manner, actual write operations directed to memory cells are delayed by one write access, so that access to the memory core can be made from the beginning of a given write operation cycle, thereby providing an interface equivalent to SRAMs in terms of the specifications of the write operation.
Further, there is a need to periodically refresh data of memory cells in the DRAMs while there is no need for refresh operations in the SRAMs. In the DRAMs that operate like SRAMs, therefore, refresh operations should be automatically performed inside the device at the proper refresh timing in such a manner that the refresh operations are concealed from outside the device. To this end, a refresh operation needs to be carried out within a single command cycle even if a write operation or a read operation is performed in the same command cycle.
In order to achieve this, the period of a core operation required for a single access may be set half as long as a minimum command input cycle. With this provision, all the necessary operations can be performed within a single command input cycle even if a refresh operation collides with a write operation or a read operation.
In the related-art, various provisions as described above were made so as to provide a DRAM having an interface equivalent to that of SRAMs.
However, the configuration as described above needs a buffer circuit for the purpose of temporarily storing data and an address, so that the larger the number of bits of input/output data is, the larger the size of the buffer circuit. Further, since the data that was last stored in the buffer is not yet written in the memory core, there is a need to access the buffer instead of the memory core when reading data that was last written. Moreover, the address that is entered from the exterior of the device is different from the core address that is being accessed. In this manner, the configuration provided with the buffer for data write operation has problems in that the circuit configuration and timing control become undesirably complicated.
Accordingly, there is a need for a semiconductor memory device that uses a DRAM memory core and provides an interface equivalent to that of SRAMs, yet does not have a buffer for the purpose of temporarily holding data and an address for write operations.